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DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4x and 8x interpolating
Rev. 01 -- 10 March 2010 Preliminary data sheet
1. General description
The DAC1405D750 is a high-speed 14-bit dual channel Digital-to-Analog Converter (DAC) with selectable 4x or 8x interpolating filters optimized for multi-carrier wireless transmitters. Thanks to its digital on-chip modulation, the DAC1405D750 allows the complex I and Q inputs to be converted from BaseBand (BB) to IF. The mixing frequency is adjusted via a Serial Peripheral Interface (SPI) with a 32-bit Numerically Controlled Oscillator (NCO) and the phase is controlled by a 16-bit register. Two modes of operation are available: separate data ports or a single interleaved high-speed data port. In the Interleaved mode, the input data stream is demultiplexed into its original I and Q data and then latched. A 4x and 8x clock multiplier enables the DAC1405D750 to provide the appropriate internal clocks from the internal PLL. The internal PLL can be bypassed enabling the use of an external high frequency clock. The voltage regulator enables adjustment of the output full-scale current.
2. Features and benefits
Dual 14-bit resolution 750 Msps maximum update rate Selectable 4x or 8x interpolation filters Input data rate up to 185 Msps Very low noise cap-free integrated PLL 32-bit programmable NCO frequency Dual port or Interleaved data modes 1.8 V and 3.3 V power supplies LVDS compatible clock Two's complement or binary offset data format 1.8 V/3.3 V CMOS input buffers IMD3: 76 dBc; fs = 737.28 Msps; fo = 140 MHz ACPR: 71 dBc; 2-carrier WCDMA; fs = 737.28 Msps; fo = 153.6 MHz Typical 1.2 W power dissipation at 4x interpolation, PLL off and 740 Msps Power-down and Sleep modes Differential scalable output current from 1.6 mA to 22 mA On-chip 1.25 V reference External analog offset control (10-bit auxiliary DACs) Internal digital offset control Inverse x / (sin x) function Fully compatible SPI port Industrial temperature range from -40 C to +85 C
NXP Semiconductors
DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4x and 8x interpolating
3. Applications
Wireless infrastructure: LTE, WiMAX, GSM, CDMA, WCDMA, TD-SCDMA Communication: LMDS/MMDS, point-to-point Direct Digital Synthesis (DDS) Broadband wireless systems Digital radio links Instrumentation Automated Test Equipment (ATE)
4. Ordering information
Table 1. Ordering information Package Name DAC1405D750HW HTQFP100 Description plastic thermal enhanced thin quad flat package; 100 leads; body 14 x 14 x 1 mm; exposed die pad Version SOT638-1 Type number
DAC1405D750_1
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Preliminary data sheet
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Preliminary data sheet Rev. 01 -- 10 March 2010 3 of 43
DAC1405D750_1
5. Block diagram
NXP Semiconductors
SDO SDIO 62
SCS_N SCLK 65 64 NCO cos sin
mixer
63 SPI
10-BIT OFFSET CONTROL 10-BIT GAIN CONTROL
+
AUXILIARY DAC
2 3
AUXAP AUXAN
DAC1405D750
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18 to 25, 28 to 31, 34, 35 I0 to I14
14
FIR1 LATCH I 2x
FIR2 2x
FIR3 2x
mixer -
90
A x sin x +
DAC A
91
IOUTAP IOUTAN
Dual 14-bit DAC, up to 750 Msps; 4x and 8x interpolating
68 dual port/ interleaved data modes FIR1 41, 42, 45 to 48, 51 to 58 Q0 to Q14
14 +
OFFSET CONTROL FIR2 2x FIR3 2x
mixer
REFERENCE BANDGAP
VIRES GAPOUT
69
LATCH Q
2x
+ B x sin x
+
86 DAC B 85
IOUTBP IOUTBN
CLKP CLKN
8 9 CLOCK GENERATOR/PLL
mixer
10-BIT GAIN CONTROL COMPLEX MODULATOR 74 AUXILIARY DAC 73
DAC1405D750
10-BIT OFFSET CONTROL
AUXBP AUXBN
001aal377
66 RESET_N
12 SYNCP
13 SYNCN
Fig 1.
Block diagram
NXP Semiconductors
DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4x and 8x interpolating
6. Pinning information
6.1 Pinning
99 VDDA(1V8) 97 VDDA(1V8) 95 VDDA(1V8) 93 VDDA(1V8) 83 VDDA(1V8) 81 VDDA(1V8) 79 VDDA(1V8) 77 VDDA(1V8) 91 IOUTAN 85 IOUTBN
90 IOUTAP
86 IOUTBP
80 AGND
98 AGND
96 AGND
92 AGND
100 AGND
78 AGND
94 AGND
89 AGND
87 AGND
84 AGND
82 AGND
VDDA(3V3) AUXAP AUXAN AGND VDDA(1V8) VDDA(1V8) AGND CLKP CLKN
1 2 3 4 5 6 7 8 9
76 AGND
88 n.c.
75 VDDA(3V3) 74 AUXBP 73 AUXBN 72 AGND 71 VDDA(1V8) 70 VDDA(1V8) 69 GAPOUT 68 VIRES 67 d.n.c. 66 RESET_N 65 SCS_N 64 SCLK
AGND 10 VDDA(1V8) 11 SYNCP 12 SYNCN 13 TM1 14 TM0 15 VDD(IO)(3V3) 16 GNDIO 17 I13 18 I12 19 I11 20 I10 21 I9 22 I8 23 I7 24 I6 25 AGND
DAC1405D750HW
63 SDIO 62 SDO 61 TM3 60 VDD(IO)(3V3) 59 GNDIO 58 Q0 57 Q1 56 Q2 55 Q3 54 Q4 53 Q5 52 Q6 51 Q7
VDDD(1V8) 26
DGND 27
I5 28
I4 29
I3 30
I2 31
VDDD(1V8) 32
DGND 33
I1 34
I0 35
VDDD(1V8) 36
DGND 37
TM2 38
DGND 39
VDDD(1V8) 40
Q13/SELIQ 41
Q12 42
DGND 43
VDDD(1V8) 44
Q11 45
Q10 46
Q9 47
Q8 48
DGND 49
VDDD(1V8) 50
001aal378
Fig 2.
Pin configuration
DAC1405D750_1
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Preliminary data sheet
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NXP Semiconductors
DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4x and 8x interpolating
6.2 Pin description
Table 2. Symbol VDDA(3V3) AUXAP AUXAN AGND VDDA(1V8) VDDA(1V8) AGND CLKP CLKN AGND VDDA(1V8) SYNCP SYNCN TM1 TM0 VDD(IO)(3V3) GNDIO I13 I12 I11 I10 I9 I8 I7 I6 VDDD(1V8) DGND I5 I4 I3 I2 VDDD(1V8) DGND I1 I0 VDDD(1V8) DGND TM2 DGND
DAC1405D750_1
Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Type[1] P O O G P P G I I G P O O I/O I/O P G I I I I I I I I P G I I I I P G I I P G G Description analog supply voltage 3.3 V auxiliary DAC B output current complementary auxiliary DAC B output current analog ground analog supply voltage 1.8 V analog supply voltage 1.8 V analog ground clock input complementary clock input analog ground analog supply voltage 1.8 V synchronous clock output complementary synchronous clock output test mode 1 (connected to DGND) test mode 0 (connected to DGND) input/output buffers supply voltage 3.3 V input/output buffers ground I data input bit 13 (MSB) I data input bit 12 I data input bit 11 I data input bit 10 I data input bit 9 I data input bit 8 I data input bit 7 I data input bit 6 digital supply voltage 1.8 V digital ground I data input bit 5 I data input bit 4 I data input bit 3 I data input bit 2 digital supply voltage 1.8 V digital ground I data input bit 1 I data input bit 0 (LSB) digital supply voltage 1.8 V digital ground test mode 2 (to connect to DGND) digital ground
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Preliminary data sheet
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NXP Semiconductors
DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4x and 8x interpolating
Pin description ...continued Pin 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Type[1] P I I G P I I I I G P I I I I I I I I G P I/O O I/O I I I I/O I/O P P G O O P G P G P G Description digital supply voltage 1.8 V Q data input bit 13 (MSB)/select IQ in Interleaved mode Q data input bit 12 digital ground digital supply voltage 1.8 V Q data input bit 11 Q data input bit 10 Q data input bit 9 Q data input bit 8 digital ground digital supply voltage 1.8 V Q data input bit 7 Q data input bit 6 Q data input bit 5 Q data input bit 4 Q data input bit 3 Q data input bit 2 Q data input bit 1 Q data input bit 0 (LSB) input/output buffers ground input/output buffers supply voltage 3.3 V test mode 3 (to connect to DGND) SPI data output SPI data input/output SPI clock input SPI chip select (active LOW) general reset (active LOW) do not connect DAC biasing resistor bandgap input/output voltage analog supply voltage 1.8 V analog supply voltage 1.8 V analog ground auxiliary DAC B output current complementary auxiliary DAC B output current analog supply voltage 3.3 V analog ground analog supply voltage 1.8 V analog ground analog supply voltage 1.8 V analog ground
(c) NXP B.V. 2010. All rights reserved.
Table 2. Symbol VDDD(1V8) Q13/SELIQ Q12 DGND VDDD(1V8) Q11 Q10 Q9 Q8 DGND VDDD(1V8) Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 GNDIO VDD(IO)(3V3) TM3 SDO SDIO SCLK SCS_N RESET_N d.n.c. VIRES GAPOUT VDDA(1V8) VDDA(1V8) AGND AUXBN AUXBP VDDA(3V3) AGND VDDA(1V8) AGND VDDA(1V8) AGND
DAC1405D750_1
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Preliminary data sheet
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NXP Semiconductors
DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4x and 8x interpolating
Pin description ...continued Pin 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 H[2] Type[1] P G P G O O G G O O G P G P G P G P G G Description analog supply voltage 1.8 V analog ground analog supply voltage 1.8 V analog ground complementary DAC B output current DAC B output current analog ground not connected analog ground DAC A output current complementary DAC A output current analog ground analog supply voltage 1.8 V analog ground analog supply voltage 1.8 V analog ground analog supply voltage 1.8 V analog ground analog supply voltage 1.8 V analog ground analog ground
Table 2. Symbol VDDA(1V8) AGND VDDA(1V8) AGND IOUTBN IOUTBP AGND n.c. AGND IOUTAP IOUTAN AGND VDDA(1V8) AGND VDDA(1V8) AGND VDDA(1V8) AGND VDDA(1V8) AGND AGND
[1]
P = power supply G = ground I = input O = output.
[2]
H = heatsink (exposed die pad to be soldered)
DAC1405D750_1
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Preliminary data sheet
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NXP Semiconductors
DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4x and 8x interpolating
7. Limiting values
Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDDA(3V3) VDDA(1V8) VDDD(1V8) VI Parameter analog supply voltage (3.3 V) analog supply voltage (1.8 V) digital supply voltage (1.8 V) input voltage pins CLKP, CLKN, VIRES and GAPOUT referenced to pin AGND pins I13 to I0, Q13 to Q0, SDO, SDIO, SCLK, SCS_N and RESET_N referenced to GNDIO VO output voltage pins IOUTAP, IOUTAN, IOUTBP, IOUTBN, AUXAP, AUXAN, AUXBP and AUXBN referenced to pin AGND pins SYNCP and SYNCN referenced to pin AGND Tstg Tamb Tj storage temperature ambient temperature junction temperature Conditions Min -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 Max +4.6 +4.6 +3.0 +3.0 +3.0 +4.6 +4.6 Unit V V V V V V V VDD(IO)(3V3) input/output supply voltage (3.3 V)
-0.5 -55 -40 -
+3.0 +150 +85 125
V C C C
8. Thermal characteristics
Table 4. Symbol Rth(j-a) Rth(j-c)
[1]
Thermal characteristics Parameter thermal resistance from junction to ambient thermal resistance from junction to case Conditions
[1] [1]
Typ 19.8 7.7
Unit K/W K/W
In compliance with JEDEC test board, in free air.
DAC1405D750_1
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Preliminary data sheet
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NXP Semiconductors
DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4x and 8x interpolating
9. Characteristics
Table 5. Characteristics VDDA(1V8) = VDDD(1V8) = 1.8 V; VDDA(3V3) = VDD(IO)(3V3) = 3.3 V; AGND, DGND and GNDIO shorted together; Tamb = -40 C to +85 C; typical values measured at Tamb = 25 C; RL = 50 differential; IO(fs) = 20 mA; PLL off unless otherwise specified. Symbol VDD(IO)(3V3) VDDA(3V3) VDDA(1V8) VDDD(1V8) IDD(IO)(3V3) Parameter input/output supply voltage (3.3 V) analog supply voltage (3.3 V) analog supply voltage (1.8 V) digital supply voltage (1.8 V) input/output supply current (3.3 V) fo = 19 MHz; fs = 740 Msps; 4x interpolation; NCO on fo = 19 MHz; fs = 740 Msps; 4x interpolation; NCO on Conditions Test[1] I I I I I Min 3.0 3.0 1.7 1.7 Typ 3.3 3.3 1.8 1.8 0.3 Max 3.6 3.6 1.9 1.9 Unit V V V V mA
IDDA(3V3)
analog supply current (3.3 V)
I
-
44

mA
IDDD(1V8)
digital supply current (1.8 V) fo = 19 MHz; fs = 740 Msps; 4x interpolation; NCO on analog supply current (1.8 V) fo = 19 MHz; fs = 740 Msps; 4x interpolation; NCO on for x / (sin x) function only
I
-
177

mA
IDDA(1V8)
I
-
350

mA
IDDD Ptot
digital supply current total power dissipation
I
-
68
-
mA
fo = 19 MHz; fs = 740 Msps 4x interpolation NCO off; DAC B off NCO off NCO on; all VDD 8x interpolation NCO on Power-down mode: full power-down; all VDD 8x interpolation DAC A and DAC B Sleep mode: NCO on I 0.63 W I 0.03 W I 1.09 W C C C 0.75 0.87 1.11 W W W
DAC1405D750_1
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NXP Semiconductors
DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4x and 8x interpolating
Table 5. Characteristics ...continued VDDA(1V8) = VDDD(1V8) = 1.8 V; VDDA(3V3) = VDD(IO)(3V3) = 3.3 V; AGND, DGND and GNDIO shorted together; Tamb = -40 C to +85 C; typical values measured at Tamb = 25 C; RL = 50 differential; IO(fs) = 20 mA; PLL off unless otherwise specified. Symbol Vi Vidth Ri Ci Vo(cm) VO(dif) Ro VIL VIH IIL IIH VIL VIH IIL IIH IO(fs) VO Ro Co EO EG VO(ref) VO(ref) IO(ref) IO(aux) VO(aux) Parameter CLKN)[2] CLKN |Vgpd| < 50 mV or C CLKP |Vgpd| < 50 mV C D D C C D C C VIL = 1.0 V VIH = 2.3 V I I C C VIL = 1.0 V VIH = 2.3 V register value = 00h default register output voltage output resistance output capacitance offset error variation gain error variation reference output voltage reference output voltage variation reference output current auxiliary output current auxiliary output voltage Tamb = 25 C compliance range I I C C C D D C C I C external voltage 1.25 V D differential outputs compliance range I C D
[3]
Conditions
Test[1]
Min 825 -100 -
Typ 10 0.5
Max 1575 +100 -
Unit mV mV M pF V V V A A V nA nA mA mA V k pF ppm/C ppm/C V ppm/C A mA V bit
Clock inputs (CLKP and
input voltage input differential threshold voltage input resistance input capacitance common mode output voltage differential output voltage output resistance LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current full-scale output current
[3]
Clock outputs (SYNCP and SYNCN) VDDA(1V8) - 0.3 1.2 80 1.0 1.0 VDDA(3V3) 1.29 2 -
Digital inputs (I0 to I13, Q0 to Q13) GNDIO 2.3 60 80 VDD(IO)(3V3) V
Digital inputs (SDO, SDIO, SCLK, SCS_N and RESET_N) GNDIO 2.3 1.8 1.2 0 20 20 1.6 20 250 3 6 18 1.25 117 40 2.2 10 VDD(IO)(3V3) V
Analog outputs (IOUTAP, IOUTAN, IOUTBP and IOUTBN)
Reference voltage output (GAPOUT)
Analog auxiliary outputs (AUXAP, AUXAN, AUXBP and AUXBN)
NDAC(aux)mono auxiliary DAC monotonicity guaranteed
DAC1405D750_1
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Preliminary data sheet
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NXP Semiconductors
DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4x and 8x interpolating
Table 5. Characteristics ...continued VDDA(1V8) = VDDD(1V8) = 1.8 V; VDDA(3V3) = VDD(IO)(3V3) = 3.3 V; AGND, DGND and GNDIO shorted together; Tamb = -40 C to +85 C; typical values measured at Tamb = 25 C; RL = 50 differential; IO(fs) = 20 mA; PLL off unless otherwise specified. Symbol fdata tw(CLK) th(i) tsu(i) SYNC signal td delay time fSYNC = fs / 4 fSYNC = fs / 8 variation Output timing fs ts fNCO sampling frequency settling time NCO frequency to 0.5 LSB register values 00000000h FFFFFFFFh fstep fNCO step frequency NCO frequency register values 00000000h F8000000h fstep SFDR step frequency spurious-free dynamic range fs = 737.28 Msps fdata = 91.6 MHz; B = fdata / 2 fo = 4 MHz; 0 dBFS fo = 19 MHz; 0 dBFS fo = 70 MHz; 0 dBFS SFDRRBW restricted bandwidth spurious-free dynamic range C I C 76 74 86 dBc dBc dBc fdata = 184.32 MHz; B = fdata / 2 Dynamic performance D D D 0 716.875 23.125 MHz MHz MHz Low-power NCO frequency range D D D 0 740 0.172 MHz MHz Hz C D 20 750 Msps ns C C C 0.21 0.3 0.27 ns ns ps/C Parameter data rate CLK pulse width input hold time input set-up time Conditions Dual-port mode input Test[1] C C C C Min 40 Typ Max 185 60 Unit MHz % ns ns Input timing (see Figure 10)
NCO frequency range
fo = 153.6 MHz; 0 dBFS; fdata = 184.32 MHz; fs = 737.28 Msps B = 20 MHz B = 100 MHz B = 20 MHz; 8-tone; 500 kHz spacing C C C 85 83 75 dBc dBc dBc
DAC1405D750_1
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Preliminary data sheet
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NXP Semiconductors
DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4x and 8x interpolating
Table 5. Characteristics ...continued VDDA(1V8) = VDDD(1V8) = 1.8 V; VDDA(3V3) = VDD(IO)(3V3) = 3.3 V; AGND, DGND and GNDIO shorted together; Tamb = -40 C to +85 C; typical values measured at Tamb = 25 C; RL = 50 differential; IO(fs) = 20 mA; PLL off unless otherwise specified. Symbol IMD3 Parameter third-order intermodulation distortion Conditions Test[1] Min Typ Max Unit
fdata = 184.32 MHz; fs = 737.28 Msps fo1 = 95 MHz; fo2 = 97 MHz fo1 = 152.5 MHz; fo2 = 153.5 MHz fo1 = 137 MHz; fo2 = 143 MHz C I C
[4]
-
77 76 76
-
dBc dBc dBc
[4]
[4]
ACPR
adjacent channel power ratio
fdata = 184.32 MHz; fs = 737.28 Msps; fo = 96 MHz 1-carrier; B = 5 MHz 2-carrier; B = 10 MHz 4-carrier; B = 20 MHz 1-carrier; B = 5 MHz 2-carrier; B = 10 MHz 4-carrier; B = 20 MHz I C C C C C 75 72 70 73 71 68 dBc dBc dBc dBc dBc dBc
fdata = 184.32 MHz; fs = 737.28 Msps; fo = 153.6 MHz
NSD
noise spectral density fdata = 184.32 MHz; fs = 737.28 Msps fo = 19 MHz; 0 dBFS C fo = 153.6 MHz; 0 dBFS; fo = 153.6 MHz; -10 dBFS C C -161 -156 -158 dBc/Hz dBc/Hz dBc/Hz
[1] [2] [3] [4]
D = guaranteed by design; C = guaranteed by characterization; I = 100 % industrially tested. CLKP and CLKN inputs are at differential LVDS levels. An external differential resistor with a value of between 80 and 120 should be connected across the pins (see Figure 8). |Vgpd| represents the ground potential difference voltage. This is the voltage that results from current flowing through the finite resistance and the inductance between the receiver and the driver circuit ground voltages. IMD3 rejection with -6 dBFS/tone.
DAC1405D750_1
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NXP Semiconductors
DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4x and 8x interpolating
10. Application information
10.1 General description
The DAC1405D750 is a dual 14-bit DAC which operates at up to 750 Msps. Each DAC consists of a segmented architecture, comprising a 6-bit thermometer sub-DAC and an 8-bit binary weighted sub-DAC. The input data rate of up to 185 MHz combined with the maximum output sampling rate of 750 Msps make the DAC1405D750 extremely flexible in wide bandwidth and multi-carrier systems. The device's quadrature modulator and 32-bit NCO simplifies system frequency selection. This is also possible because the 4x and 8x interpolation filters remove undesired images. A SYNC signal is provided to synchronize data when the PLL is in the off state. Two modes are available for the digital input. In Dual-port mode, each DAC uses its own data input line. In Interleaved mode, both DACs use the same data input line. The on-chip PLL enables generation of the internal clock signals for the digital circuitry and the DAC from a low speed clock. The PLL can be bypassed enabling the use of an external, high-speed clock. Each DAC generates two complementary current outputs on pins IOUTAP/IOUTAN and IOUTBP/IOUTBN. This provides a full-scale output current (IO(fs)) up to 22 mA. An internal reference is available for the reference current which is externally adjustable using pin VIRES. There are also some embedded features to provide an analog offset correction (auxiliary DACs) and digital offset control as well as for gain adjustment. All the functions can be set using the SPI. The DAC1405D750 operates at both 3.3 V and 1.8 V each of which has separate digital and analog power supplies. The digital input is 1.8 V and 3.3 V compliant and the clock input is LVDS compliant.
10.2 Serial peripheral interface
10.2.1 Protocol description
The DAC1405D750 Serial Peripheral Interface (SPI) is a synchronous serial communication port allowing easy interfacing with many industry microprocessors. It provides access to the registers that define the operating modes of the chip in both write and read modes. This interface can be configured as a 3-wire type (SDIO as a bidirectional pin) or a 4-wire type (SDIO and SDO as unidirectional pins, input and output port respectively). In both configurations, SCLK acts as the serial clock and SCS_N acts as the serial chip select bar. Each read/write operation is sequenced by the SCS_N signal and enabled by a LOW assertion to drive the chip with 1 to 4 bytes, depending on the content of the instruction byte (see Table 7).
DAC1405D750_1
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DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4x and 8x interpolating
RESET_N (optional) SCS_N
SCLK
SDIO SDO (optional)
R/W
N1
N0
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
001aaj812
R/W indicates the mode access, (see Table 6)
Fig 3.
SPI protocol Table 6. R/W 0 1 Read or Write mode access description Description Write mode operation Read mode operation
In Table 7 N1 and N0 indicate the number of bytes transferred after the instruction byte.
Table 7. N1 0 0 1 1 Number of bytes transferred N0 0 1 0 1 Number of bytes 1 byte transferred 2 bytes transferred 3 bytes transferred 4 bytes transferred
A0 to A4: indicate which register is being addressed. In the case of a multiple transfer, this address concerns the first register after which the next registers follow directly in a decreasing order according to Table 9 "Register allocation map".
10.2.2 SPI timing description
The interface can operate at a frequency of up to 15 MHz. The SPI timing is shown in Figure 4.
tw(RESET_N) RESET_N (optional) SCS_N 50 % tsu(SCS_N) 50 % tw(SCLK) SCLK 50 % th(SCS_N)
SDIO
50 % th(SDIO) tsu(SDIO)
001aaj813
Fig 4.
DAC1405D750_1
SPI timing diagram
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Preliminary data sheet
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NXP Semiconductors
DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4x and 8x interpolating
The SPI timing characteristics are given in Table 8.
Table 8. Symbol fSCLK tw(SCLK) tsu(SCS_N) th(SCS_N) tsu(SDIO) th(SDIO) tw(RESET_N) SPI timing characteristics Parameter SCLK frequency SCLK pulse width SCS_N set-up time SCS_N hold time SDIO set-up time SDIO hold time RESET_N pulse width Min 30 20 20 10 5 30 Typ Max 15 Unit MHz ns ns ns ns ns ns
10.2.3 Detailed descriptions of registers
An overview of the details for all registers is provided in Table 9.
DAC1405D750_1
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Table 9. Address Dec Hex 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 26 27 28 29 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h
Register allocation map Register name COMMon TXCFG PLLCFG FREQNCO_LSB FREQNCO_LISB FREQNCO_UISB FREQNCO_MSB PHINCO_LSB PHINCO_MSB DAC_A_Cfg_1 R/W Bit definition Bit 7 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W DAC_A_PD R/W R/W DAC_A_ SLEEP 3W_SPI NCO_ON PLL_PD Bit 6 SPI_RST NCO_LP_ SEL Bit 5 CLK_SEL INV_SIN_ SEL PLL_DIV_ PD Bit 4 Bit 3 MODE_ SEL Bit 2 CODING Bit 1 IC_PD Bit 0 GAP_PD Default Bin 10000000 10000111 Dec Hex 128 80 135 87 16 10
MODULATION[2:0] PLL_DIV[1:0] FREQ_NCO[7:0] FREQ_NCO[15:8] FREQ_NCO[23:16] FREQ_NCO[31:24] PH_NCO[7:0] PH_NCO[15:8]
INTERPOLATION[1:0]
DAC_CLK_DELAY[1:0]
DAC_CLK 00010000 _POL 01100110 01100110 01100110 00100110 00000000 00000000 00000000 01000000 11000000 00000000 01000000 11000000 NOISE_ SHPER 00000000 00000000 10000000
102 66 102 66 102 66 38 0 0 0 64 26 00 00 00
DAC_A_OFFSET[5:0] DAC_A_GAIN_FINE[5:0] DAC_A_OFFSET[11:6] DAC_B_OFFSET[5:0] DAC_B_GAIN_FINE[5:0] DAC_B_OFFSET[11:6] MINUS_ 3DB AUX_A[9:2] AUX_B[9:2] AUX_B[1:0] AUX_A[1:0]
Dual 14-bit DAC, up to 750 Msps; 4x and 8x interpolating
0Ah DAC_A_Cfg_2 0Bh DAC_A_Cfg_3 0Ch DAC_B_Cfg_1 0Dh DAC_B_Cfg_2 0Eh DAC_B_Cfg_3 0Fh 10h DAC_Cfg SYNC_Cfg
DAC_A_GAIN_ COARSE[1:0] DAC_A_GAIN_ COARSE[3:2] DAC_B_ SLEEP
40
192 C0 0 64 00 40
R/W DAC_B_PD R/W R/W R/W R/W SYNC_DIV
DAC_B_GAIN_ COARSE[1:0] DAC_B_GAIN_ COARSE[3:2]
192 C0 0 0 0 0 00 00 00 00
DAC1405D750
SYNC_SEL
1Ah DAC_A_Aux_MSB R/W 1Bh DAC_A_Aux_LSB R/W AUX_A_PD 1Ch DAC_B_Aux_MSB R/W 1Dh DAC_B_Aux_LSB R/W AUX_B_PD
128 80 128 80
00000000 10000000 00000000
NXP Semiconductors
DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4x and 8x interpolating
10.2.4 Detailed register descriptions
Please refer to Table 9 for the register overview and relevant default values. In the following tables, all the values shown in bold are the default values.
Table 10. COMMon register (address 00h) bit description Default settings are shown highlighted. Bit 7 Symbol 3W_SPI Access Value Description R/W 0 1 6 SPI_RST R/W 0 1 5 CLK_SEL R/W 0 1 4 3 MODE_SEL R/W 0 1 2 CODING R/W 0 1 1 IC_PD R/W 0 1 0 GAP_PD R/W 0 1 serial interface bus type 4 wire SPI 3 wire SPI serial interface reset no reset performs a reset on all registers except 00h data input latch at CLK rising edge at CLK falling edge reserved input data mode dual port interleaved coding binary two's compliment power-down disabled all circuits (digital and analog, except SPI) are switched off internal bandgap power-down power-down disabled internal bandgap references are switched off
Table 11. TXCFG register (address 01h) bit description Default settings are shown highlighted. Bit 7 Symbol NCO_ON Access Value Description R/W 0 1 6 NCO_LP_SEL R/W 0 1 NCO disabled (the NCO phase is reset to 0) enabled low-power NCO disabled NCO frequency and phase given by the five MSBs of the registers 06h and 08h respectively x / (sin x) function 0 1
DAC1405D750_1
5
INV_SIN_SEL
R/W
disabled enabled
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DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4x and 8x interpolating
Table 11. TXCFG register (address 01h) bit description ...continued Default settings are shown highlighted. Bit Symbol Access Value Description R/W 000 001 010 011 100 1 to 0 INTERPOLATION[1:0] R/W 01 10 11 modulation dual DAC: no modulation positive upper single sideband up-conversion positive lower single sideband up-conversion negative upper single sideband up-conversion negative lower single sideband up-conversion interpolation reserved 4x 8x 4 to 2 MODULATION[2:0]
Table 12. PLLCFG register (address 02h) bit description Default settings are shown highlighted. Bit 7 Symbol PLL_PD Access Value Description PLL ON R/W 0 1 6 5 PLL_DIV_PD R/W 0 1 4 to 3 PLL_DIV[1:0] R/W 00 01 10 11 2 to 1 DAC_CLK_DELAY[1:0] R/W 00 01 10 0 DAC_CLK_POL R/W 0 1 Table 13. Bit 7 to 0 reserved PLL divider switched on switched off PLL divider factor 2 4 8 X phase shift (fs) 0 120 240 clock edge of DAC (fs) normal inverted undefined X X Digital clock delay 130 ps 280 ps 430 ps 580 ps undefined X X X undefined X X PLL switched on switched off PLL OFF
FREQNCO_LSB register (address 03h) bit description Access Value Description R/W lower 8 bits for the NCO frequency setting
Symbol FREQ_NCO[7:0]
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DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4x and 8x interpolating
FREQNCO_LISB register (address 04h) bit description Access Value Description R/W lower intermediate 8 bits for the NCO frequency setting
Table 14. Bit 7 to 0
Symbol FREQ_NCO[15:8]
Table 15. Bit 7 to 0
FREQNCO_UISB register (address 05h) bit description Access Value Description R/W upper intermediate 8 bits for the NCO frequency setting
Symbol FREQ_NCO[23:16]
Table 16. Bit 7 to 0
FREQNCO_MSB register (address 06h) bit description Access Value Description R/W most significant 8 bits for the NCO frequency setting
Symbol FREQ_NCO[31:24]
Table 17. Bit 7 to 0
PHINCO_LSB register (address 07h) bit description Access Value Description R/W lower 8 bits for the NCO phase setting
Symbol PH_NCO[7:0]
Table 18. Bit 7 to 0
PHINCO_MSB register (address 08h) bit description Access Value Description R/W most significant 8 bits for the NCO phase setting
Symbol PH_NCO[15:8]
Table 19. DAC_A_Cfg_1 register (address 09h) bit description Default settings are shown highlighted. Bit 7 Symbol DAC_A_PD Access Value Description R/W 0 1 6 DAC_A_SLEEP R/W 0 1 5 to 0 DAC_A_OFFSET[5:0] R/W DAC A power on off DAC A Sleep mode disabled enabled lower 6 bits for the DAC A offset
Table 20. Bit 7 to 6 5 to 0
DAC_A_Cfg_2 register (address 0Ah) bit description Access Value Description R/W R/W lower 2 bits for the DAC A gain setting for coarse adjustment lower 6 bits for the DAC A gain setting for fine adjustment
Symbol DAC_A_GAIN_ COARSE[1:0] DAC_A_GAIN_ FINE[5:0]
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DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4x and 8x interpolating
DAC_A_Cfg_3 register (address 0Bh) bit description Access Value R/W R/W Description most significant 2 bits for the DAC A gain setting for coarse adjustment most significant 6 bits for the DAC A offset
Table 21. Bit 7 to 6 5 to 0
Symbol DAC_A_GAIN_ COARSE[3:2] DAC_A_ OFFSET[11:6]
Table 22. DAC_B_Cfg_1 register (address 0Ch) bit description Default settings are shown highlighted. Bit 7 Symbol DAC_B_PD Access Value Description R/W 0 1 6 DAC_B_SLEEP R/W 0 1 5 to 0 DAC_B_OFFSET[5:0] R/W DAC B power on off DAC B Sleep mode disabled enabled lower 6 bits for the DAC B offset
Table 23. Bit 7 to 6 5 to 0
DAC_B_Cfg_2 register (address 0Dh) bit description Access Value Description R/W R/W less significant 2 bits for the DAC B gain setting for coarse adjustment the 6 bits for the DAC B gain setting for fine adjustment
Symbol DAC_B_GAIN_ COARSE[1:0] DAC_B_GAIN_ FINE[5:0]
Table 24. Bit 7 to 6 5 to 0
DAC_B_Cfg_3 register (address 0Eh) bit description Access Value Description R/W R/W most significant 2 bits for the DAC B gain setting for coarse adjustment most significant 6 bits for the DAC B offset
Symbol DAC_B_GAIN_ COARSE[3:2] DAC_B_ OFFSET[11:6]
Table 25. DAC_Cfg register (address 0Fh) bit description Default settings are shown highlighted. Bit 1 Symbol MINUS_3DB Access Value R/W 0 1 0 NOISE_SHPER R/W 0 1 Description reserved NCO gain unity -3 dB noise shaper disabled enabled 7 to 2 -
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DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4x and 8x interpolating
Table 26. SYNC_Cfg register (address 10h) bit description Default settings are shown highlighted. Bit 7 Symbol SYNC_DIV Access Value R/W 0 1 6 SYNC_SEL R/W 0 1 5 to 0 Table 27. Bit Description fs divided by 4 8 SYNC selection disabled enabled reserved
DAC_A_Aux_MSB register (address 1Ah) bit description Access Value R/W Description most significant 8 bits for the auxiliary DAC A
Symbol
7 to 0 AUX_A[9:2]
Table 28. DAC_A_Aux_LSB register (address 1Bh) bit description Default settings are shown highlighted. Bit 7 Symbol AUX_A_PD Access Value R/W 0 1 6 to 1 1 to 0 AUX_A[1:0] Table 29. Bit R/W Description auxiliary DAC A power on off reserved lower 2 bits for the auxiliary DAC A
DAC_B_Aux_MSB register (address 1Ch) bit description Access Value R/W Description most significant 8 bits for the auxiliary DAC B
Symbol
7 to 0 AUX_B[9:2]
Table 30. DAC_B_Aux_LSB register (address 1Dh) bit description Default settings are shown highlighted. Bit 7 Symbol AUX_B_PD Access Value R/W 0 1 6 to 1 1 to 0 AUX_B[1:0] R/W Description auxiliary DAC B power on off reserved lower 2-bits for the auxiliary DAC B
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DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4x and 8x interpolating
10.2.5 Recommended configuration
It is recommended that the following additional settings are used to obtain optimum performance at up to 750 Msps
Table 31. Address Dec 17 19 20 Hex 11h 13h 14h Recommended configuration Value Bin 00001010 01101100 01101100 Dec 10 108 108 Hex 0Ah 6Ch 6Ch
10.3 Input data
The setting applied to MODE_SEL (register 00h[3]; see Table 10 on page 17) defines whether the DAC1405D750 operates in the Dual-port mode or in Interleaved mode (see Table 32).
Table 32. 0 1 Mode selection Function Dual port mode Interleaved mode I13 to I0 active active Q13 to Q0 active off Pin 41 Q13 SELIQ
Bit 3 setting
10.3.1 Dual-port mode
The data input for Dual-port mode operation is shown in Figure 5 "Dual-port mode". Each DAC has its own independent data input. The data enters the input latch on the rising edge of the internal clock signal and is transferred to the DAC latch.
FIR 1 I13 to I0 LATCH I 2x
FIR 2 2x
FIR 3 2x
FIR 1 Q13 to Q0 LATCH Q 2x
FIR 2 2x
FIR 3 2x
001aal653
Fig 5.
Dual-port mode
10.3.2 Interleaved mode
The data input for the Interleaved mode operation is illustrated in Figure 6 "Interleaved mode operation".
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DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4x and 8x interpolating
FIR 1 LATCH I 2x
FIR 2 2x
FIR 3 2x
I13 to I0 FIR 1 Q13/SELIQ LATCH Q 2x FIR 2 2x FIR 3 2x
001aal654
Fig 6.
Interleaved mode operation
In Interleaved mode, both DACs use the same data input at twice the Dual-port mode frequency. Data enters the latch on the rising edge of the internal clock signal. The data is sent to either latch I or latch Q, depending on the SELIQ signal. The SELIQ input (pin 41) allows the synchronization of the internally demultiplexed I and Q channels; see Figure 7 "Interleaved mode timing (8x interpolation, latch on rising edge)".
In SELIQ (synchronous alternative) SELIQ (asynchronous alternative 1) SELIQ (asynchronous alternative 2) CLKdig Latch I output
N
N+1
N+2
N+3
N+4
N+5
XX
N
N+2
Latch Q output
XX
N+1
N+3
001aaj814
CLKdig = internal digital clock
Fig 7.
Interleaved mode timing (8x interpolation, latch on rising edge)
The SELIQ signal can be either synchronous or asynchronous (single rising edge, single pulse). The first data following the SELIQ rising edge is sent in channel I and following data is sent in channel Q. After this, data is distributed alternately between these channels.
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DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4x and 8x interpolating
10.4 Input clock
The DAC1405D750 can operate at the following clock frequencies: PLL on: up to 185 MHz in Dual-port mode and up to 370 MHz in Interleaved mode PLL off: up to 750 MHz The input clock is LVDS compliant (see Figure 8) but it can also be interfaced with CML differential sine wave signal (see Figure 9).
Z = 50
CLKP
LVDS
Zdiff = 100
LVDS
Z = 50
CLKN
001aah021
Fig 8.
LVDS clock configuration
VDDA(1V8)
1.1 k Z = 50 100 nF
CLKP
55
CML
Zdiff = 100 55 100 nF
LVDS
Z = 50
CLKN
2.2 k
100 nF
AGND
001aah020
Fig 9.
Interfacing CML to LVDS
10.5 Timing
The DAC1405D750 can operate at a sampling frequency (fs) up to 750 Msps with an input data rate (fdata) up to 185 MHz. When using the internal PLL, the input data is referenced to the CLK signal. When the internal PLL is bypassed, the SYNC signal is used as a reference. The input timing in the second case is shown in Figure 10 "Input timing diagram when internal PLL bypassed (off)".
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DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4x and 8x interpolating
tsu(i) I13 to I0/ Q13 to Q0 SYNC (SYNCP - SYNCN) 90 % N
th(i) 90 % N+1 N+2
50 %
001aal384
Fig 10. Input timing diagram when internal PLL bypassed (off)
10.5.1 Timing when using the internal PLL (PLL on)
In Table 33 "Frequencies", the links between internal and external clocking are defined. The setting applied to PLL_DIV[1:0] (register 02h[4:3]; see Table 9 "Register allocation map") allows the frequency between the digital part and the DAC core to be adjusted.
Table 33. Mode Dual Port Dual Port Interleaved Interleaved Frequencies CLK input Input data rate (MHz) (MHz) 185 92.5 370 185 185 92.5 370 185 Interpolation 4x 8x 4x 8x Update rate (Msps) 740 740 740 740 PLL_DIV[1:0] 01 (/ 4) 10 (/ 8) 00 (/ 2) 01 (/ 4)
The settings applied to DAC_CLK_DELAY[1:0] (register 02h[2:1]) and DAC_CLK_POL (register 02h[0]), allow adjustment of the phase and polarity of the sampling clock. This occurs at the input of the DAC core and depends mainly on the sampling frequency. Some examples are given in Table 34 "Sample clock phase and polarity examples".
Table 34. Mode Dual Port Dual Port Sample clock phase and polarity examples Input data rate (MHz) 92.5 92.5 Interpolation 4x 8x Update rate (Msps) 370 740 DAC_CLK_ DELAY [1:0] 01 01 DAC_CLK_ POL 0 0
10.5.2 Timing when using an external PLL (PLL off)
It is recommended that a delay of 280 ps is used on the internal digital clock (CLKdig) to obtain optimum device performance up to750 Msps.
Table 35. Address Dec 2 Hex 02h PLLCFG Optimum external PLL timing settings Register name Value Digital clock delay Bin 280 ps 10001000 Dec 136 Hex 88h
10.6 FIR filters
The DAC1405D750 integrates three selectable Finite Impulse Response (FIR) filters which enables the device to use 4x or 8x interpolation rates. All three interpolation filters have a stop-band attenuation of at least 80 dBc and a pass-band ripple of less than 0.0005 dB. The coefficients of the interpolation filters are given in Table 36 "Interpolation filter coefficients".
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DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4x and 8x interpolating
Interpolation filter coefficients Second interpolation filter Lower H(1) H(2) H(3) H(4) H(5) H(6) H(7) H(8) H(9) H(10) H(11) H(12) Upper H(23) H(22) H(21) H(20) H(19) H(18) H(17) H(16) H(15) H(14) H(13) Value -2 0 17 0 -75 0 238 0 -660 0 2530 4096 Third interpolation filter Lower H(1) H(2) H(3) H(4) H(5) H(6) H(7) H(8) Upper H(15) H(14) H(13) H(12) H(11) H(10) H(9) Value -39 0 273 0 -1102 0 4964 8192 Upper H(55) H(54) H(53) H(52) H(51) H(50) H(49) H(48) H(47) H(46) H(45) H(44) H(43) H(42) H(41) H(40) H(39) H(38) H(37) H(36) H(35) H(34) H(33) H(32) H(31) H(30) H(29) Value -4 0 13 0 -34 0 72 0 -138 0 245 0 -408 0 650 0 -1003 0 1521 0 -2315 0 3671 0 -6642 0 20756 32768
Table 36. Lower H(1) H(2) H(3) H(4) H(5) H(6) H(7) H(8) H(9) H(10) H(11) H(12) H(13) H(14) H(15) H(16) H(17) H(18) H(19) H(20) H(21) H(22) H(23) H(24) H(25) H(26) H(27) H(28)
First interpolation filter
10.7 Quadrature modulator and Numerically Controlled Oscillator
The quadrature modulator allows the 14-bit I and Q-data to be mixed with the carrier signal generated by the NCO. The frequency of the Numerically Controlled Oscillator (NCO) is programmed over 32-bit and allows the sign of the sine component to be inverted in order to operate positive or negative, lower or upper single sideband up-conversion.
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DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4x and 8x interpolating
10.7.1 NCO in 32-bit
When using the NCO, the frequency can be set by the four registers FREQNCO_LSB, FREQNCO_LISB, FREQNCO_UISB and FREQNCO_MSB over 32 bits. The frequency for the NCO in 32-bit is calculated as follows: M x fs f NCO = -------------32 2 where M is the decimal representation of FREQ_NCO[31:0]. The phase of the NCO can be set from 0 to 360 by both registers PHINCO_LSB and PHINCO_MSB over 16 bits. (1)
10.7.2 Low-power NCO
When using the low-power NCO, the frequency can be set by the 5 MSB of register FREQNCO_MSB. The frequency for the low-power NCO is calculated as follows: M x fs f NCO = -------------5 2 where M is the decimal representation of FREQ_NCO[31:27]. The phase of the low-power NCO can be set by the 5 MSB of the register PHINCO_MSB. (2)
10.7.3 Minus_3dB function
During normal use, a full-scale pattern will also be full scale at the output of the DAC. Nevertheless, when the I and Q data are simultaneously close to full scale, some clipping can occur and the Minus_3dB function can be used to reduce the gain by 3 dB in the modulator. This is to keep a full-scale range at the output of the DAC without added interferers.
10.8 x / (sin x)
Due to the roll-off effect of the DAC, a selectable FIR filter is inserted to compensate for the x / (sin x) effect. This filter introduces a DC loss of 3.4 dB. The coefficients are represented in Table 37 "Inversion filter coefficients".
Table 37. Lower H(1) H(2) H(3) H(4) H(5) Inversion filter coefficients Upper H(9) H(8) H(7) H(6) Value 2 -4 10 -35 401
First interpolation filter
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10.9 DAC transfer function
The full-scale output current for each DAC is the sum of the two complementary current outputs: I O ( fs ) = I IOUTP + I IOUTN The output current depends on the digital input data: DATA I IOUTP = I O ( fs ) x --------------- 16383 16383 - DATA I IOUTN = I O ( fs ) x ------------------------------------ 16383 (4) (3)
(5)
The setting applied to CODING (register 00h[2]; see Table 9 "Register allocation map") defines whether the DAC1405D750 operates with a binary input or a two's complement input. Table 38 "DAC transfer function" shows the output current as a function of the input data, when IO(fs) = 20 mA.
Table 38. Data 0 ... 8192 ... 16383 DAC transfer function I13 to I0 and Q13 to Q0 Binary 00 0000 0000 0000 ... 10 0000 0000 0000 ... 11 1111 1111 1111 Two's complement 00 0000 0000 0000 ... 00 0000 0000 0000 ... 01 1111 1111 1111 0 ... 10 ... 20 20 ... 10 ... 0 IOUTP (mA) IOUTN (mA)
10.10 Full-scale current
10.10.1 Regulation
The DAC1405D750 reference circuitry integrates an internal bandgap reference voltage which delivers a 1.25 V reference to the GAPOUT pin. It is recommended to decouple pin GAPOUT using a 100 nF capacitor. The reference current is generated via an external resistor of 910 (1 %) connected to pin VIRES. A control amplifier sets the appropriate full-scale output current (IO(fs)) for both DACs (see Figure 11 "Internal reference configuration").
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DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4x and 8x interpolating
REF. BANDGAP
100 nF
AGND
910 (1 %)
GAPOUT
AGND
VIRES
DAC CURRENT SOURCES ARRAY
001aaj816
Fig 11. Internal reference configuration
This configuration is optimum for temperature drift compensation because the bandgap reference voltage can be matched to the voltage across the feedback resistor. The DAC current can also be set by applying an external reference voltage to the non-inverting input pin GAPOUT and disabling the internal bandgap reference voltage with GAP_PD (register 00h[0]; see Table 10 "COMMon register (address 00h) bit description").
10.10.2 Full-scale current adjustment
The default full-scale current (IO(fs)) is 20 mA but further adjustments can be made by the user to both DACs independently via the serial interface from 1.6 mA to 22 mA, 10 %. The settings applied to DAC_A_GAIN_COARSE[3:0] (see Table 20 "DAC_A_Cfg_2 register (address 0Ah) bit description" and Table 21 "DAC_A_Cfg_3 register (address 0Bh) bit description") and to DAC_B_GAIN COARSE[3:0] (see Table 23 "DAC_B_Cfg_2 register (address 0Dh) bit description" and Table 24 "DAC_B_Cfg_3 register (address 0Eh) bit description") define the coarse variation of the full-scale current (see Table 39 "IO(fs) coarse adjustment").
Table 39. IO(fs) coarse adjustment Default settings are shown highlighted. DAC_GAIN_COARSE[3:0] Decimal 0 1 2 3 4 5 6 7 8 9 10 11
DAC1405D750_1
IO(fs) (mA) Binary 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1.6 3.0 4.4 5.8 7.2 8.6 10.0 11.4 12.8 14.2 15.6 17.0
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Dual 14-bit DAC, up to 750 Msps; 4x and 8x interpolating
Table 39. IO(fs) coarse adjustment ...continued Default settings are shown highlighted. DAC_GAIN_COARSE[3:0] Decimal 12 13 14 15 Binary 1100 1101 1110 1111 18.5 20.0 21.0 22.0 IO(fs) (mA)
The settings applied to DAC_A_GAIN_FINE[5:0] (see Table 20 "DAC_A_Cfg_2 register (address 0Ah) bit description") and to DAC_B_GAIN_FINE[5:0] (see Table 23 "DAC_B_Cfg_2 register (address 0Dh) bit description") define the fine variation of the full-scale current (see Table 40 "IO(fs) fine adjustment").
Table 40. IO(fs) fine adjustment Default settings are shown highlighted. DAC_GAIN_FINE[5:0] Decimal -32 ... 0 ... 31 Two's complement 10 0000 ... 00 0000 ... 01 1111 -10.3 % ... 0 ... +10 % Delta IO(fs)
The coding of the fine gain adjustment is two's complement.
10.11 Digital offset adjustment
When the DAC1405D750 analog output is DC connected to the next stage, the digital offset correction can be used to adjust the common mode level at the output of the DAC. It adds an offset at the end of the digital part, just before the DAC. The settings applied to DAC_A_OFFSET[11:0] (see Table 19 "DAC_A_Cfg_1 register (address 09h) bit description" and Table 21 "DAC_A_Cfg_3 register (address 0Bh) bit description") and to "DAC_B_OFFSET[11:0]" (see Table 22 "DAC_B_Cfg_1 register (address 0Ch) bit description" and Table 24 "DAC_B_Cfg_3 register (address 0Eh) bit description") define the range of variation of the digital offset (see Table 41 "Digital offset adjustment").
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DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4x and 8x interpolating
Table 41. Digital offset adjustment Default settings are shown highlighted. DAC_OFFSET[11:0] Decimal -2048 -2047 ... -1 0 +1 ... +2046 +2047 Two's complement 1000 0000 0000 1000 0000 0001 ... 1111 1111 1111 0000 0000 0000 0000 0000 0001 ... 0111 1111 1110 0111 1111 1111 -4096 -4094 ... -2 0 +2 ... +4092 +4094 Offset applied
10.12 Analog output
The DAC1405D750 has two output channels each of which produces two complementary current outputs. These allow the even-order harmonics and noise to be reduced. The pins are IOUTAP/IOUTAN and IOUTBP/IOUTBN, respectively and need to be connected via a load resistor RL to the 3.3 V analog power supply (VDDA(3V3)). Refer to Figure 12 for the equivalent analog output circuit of one DAC. This circuit consists of a parallel combination of NMOS current sources, and their associated switches, for each segment.
VDDA(3V3)
RL
RL
IOUTAP/IOUTBP IOUTAN/IOUTBN
AGND
AGND
001aah019
Fig 12. Equivalent analog output circuit (one DAC)
The cascode source configuration increases the output impedance of the source, thus improving the dynamic performance of the DAC by introducing less distortion. The device can provide an output level of up to 2 Vo(p-p) depending on the application, the following stages and the targeted performances.
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DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4x and 8x interpolating
10.13 Auxiliary DACs
The DAC1405D750 integrates 2 auxiliary DACs that can be used to compensate for any offset between the DAC and the next stage in the transmission path. Both auxiliary DACs have a resolution of 10-bit and are current sources (referenced to ground). I O ( AUX ) = I AUXP + I AUXN The output current depends on the auxiliary DAC data: AUX [ 9:0 ] AUXP = I O ( AUX ) x ------------------------ 1023 (1023 - A UX [ 9:0 ] ) AUXN = I O ( AUX ) x -------------------------------------------- 1023 Table 42 "Auxiliary DAC transfer function" shows the output current as a function of the auxiliary DAC data.
Table 42. Auxiliary DAC transfer function Default settings are shown highlighted. Data 0 ... 512 ... 1023 AUX[9:0] (binary) 00 0000 0000 ... 10 0000 0000 ... 11 1111 1111 IAUXP (mA) 0 ... 1.1 ... 2.2 IAUXN (mA) 2.2 ... 1.1 ... 0
(6)
(7)
(8)
10.14 Output configuration
10.14.1 Basic output configuration
The use of a differentially-coupled transformer output provides optimum distortion performance (see Figure 13 "1 Vo(p-p) differential output with transformer"). In addition, it helps to match the impedance and provides electrical isolation.
VDDA(3V3)
50 2:1
0 mA to 20 mA IOUTnP 0 mA to 20 mA IOUTnN
50
50
VDDA(3V3) IOUTnP/IOUTnN; Vo(cm) = 2.8 V; Vo(dif)(p-p) = 1 V
001aaj817
Fig 13. 1 Vo(p-p) differential output with transformer
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DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4x and 8x interpolating
The DAC1405D750 differential outputs can operate up to 2 Vo(p-p). In this configuration, it is recommended to connect the center tap of the transformer to a 62 resistor connected to the 3.3 V analog power supply, in order to adjust the DC common mode to approximately 2.7 V (see Figure 14).
VDDA(3V3)
100
VDDA(3V3)
62 4:1
0 mA to 20 mA IOUTnP 0 mA to 20 mA IOUTnN
100 50
VDDA(3V3) IOUTnP/IOUTnN; Vo(cm) = 2.7 V; Vo(dif)(p-p) = 2 V
001aaj818
Fig 14. 2 Vo(p-p) differential output with transformer
10.14.2 DC interface to an Analog Quadrature Modulator (AQM)
When the system operation requires to keep the DC component of the spectrum, the DAC1405D750 can use a DC interface to connect to an AQM. In this case, the offset compensation for LO cancellation can be made with the use of the digital offset control in the DAC. Figure 15 provides an example of a connection to an AQM with a 1.7 VI(cm) common mode input level.
VDDA(3V3)
AQM (Vi(cm) = 1.7 V)
(1)
51.1
51.1 442
(2)
IOUTnP
442
BBP BBN 0 mA to 20 mA
768 768
IOUTnN
(1) IOUTnP/IOUTnN; V o(cm) = 2.67 V; Vo(dif)(p-p) = 1.98 V (2) BBP/BBN; V i(cm) = 1.7 V; Vi(dif)(p-p) = 1.26 V 001aaj541
Fig 15. An example of a DC interface to a 1.7 VI(cm) AQM
Figure 16 provides an example of a connection to an AQM with a 3.3 VI(cm) common mode input level.
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DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4x and 8x interpolating
VDDA(3V3)
5V
AQM (Vi(cm) = 3.3 V)
(1)
54.9
54.9 237
750
750
(2)
IOUTnP
237
BBP BBN
1.27 k 1.27 k
IOUTnN
(1) IOUTnP/IOUTnN; V o(cm) = 2.75 V; Vo(dif)(p-p) = 1.97 V (2) BBP/BBN; V i(cm) = 3.3 V; Vi(dif)(p-p) = 1.5 V 001aaj542
Fig 16. An example of a DC interface to a 3.3 VI(cm) AQM
The auxiliary DACs can be used to control the offset in a precise range or with precise steps. Figure 17 provides an example of a DC interface with the auxiliary DACs to an AQM with a 1.7 VI(cm) common mode input level.
VDDA(3V3)
AQM (Vi(cm) = 1.7 V)
(1)
51.1
51.1 442
(2)
IOUTnP
442
BBP BBN 0 mA to 20 mA
698 698
IOUTnN
AUXnP AUXnN 1.1 mA (typ.)
51.1 51.1
(1) IOUTnP/IOUTnN; V o(cm) = 2.67 V; Vo(dif)(p-p) = 1.94 V (2) BBP/BBN; V i(cm) = 1.7 V; Vi(dif)(p-p) = 1.23 V; offset correction up to 50 mV 001aal655
Fig 17. An example of a DC interface to a 1.7 VI(cm) AQM using auxiliary DACs
Figure 18 provides an example of a DC interface with the auxiliary DACs to an AQM with a 3.3 VI(cm) common mode input level.
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DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4x and 8x interpolating
VDDA(3V3)
5V
AQM (Vi(cm) = 3.3 V)
(1)
54.9
54.9 237
750
750
(2)
IOUTnP
237
BBP BBN
634 k 634 k
IOUTnN
AUXnP AUXnN
442 k 442 k
(1) IOUTnP/IOUTnN; V o(cm) = 2.75 V; Vo(dif)(p-p) = 1.96 V (2) BBP/BBN; V i(cm) = 3.3 V; Vi(dif)(p-p) = 1.5 V; offset correction up to 36 mV 001aaj544
Fig 18. An example of a DC interface to a 3.3 VI(cm) AQM using auxiliary DACs
The constraints to adjust the interface are the output compliance range of the DAC and the auxiliary DACs, the input common mode level of the AQM, and the range of offset correction.
10.14.3 AC interface to an Analog Quadrature Modulator (AQM)
When the AQM common mode voltage is close to ground, the DAC1405D750 must be AC-coupled and the auxiliary DACs are needed for offset correction. Figure 18 provides an example of a connection to an AQM with a 0.5 VI(cm) common mode input level using auxiliary DACs.
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DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4x and 8x interpolating
VDDA(3V3)
5V
AQM (Vi(cm) = 0.5 V)
(1)
66.5
66.5 10 nF
2 k
2 k
(2)
IOUTnP
10 nF
BBP BBN 0 mA to 20 mA
174 174
IOUTnN
AUXnP AUXnN 1.1 mA (typ.)
34 34
(1) IOUTnP/IOUTnN; V o(cm) = 2.65 V; Vo(dif)(p-p) = 1.96 V (2) BBP/BBN; V i(cm) = 0.5 V; Vi(dif)(p-p) = 1.96 V; offset correction up to 70 mV 001aaj589
Fig 19. An example of an AC interface to a 0.5 VI(cm) AQM using auxiliary DACs
10.15 Power and grounding
In order to obtain optimum performance, it is recommended that the 1.8 V analog power supplies on pins 5, 11, 71, 77 and 99 should not be connected with the ones on pins 6, 70, 79, 81, 83, 93, 95 and 97 on the top layer. To optimize the decoupling, the power supplies should be decoupled with the following ground pins:
* VDDD(1V8): pin 26 with 27; pin 32 with 33; pin 36 with 37; pin 40 with 39; pin 44 with 43
and pin 50 with 49.
* VDD(IO)(3V3): pin 16 with 17 and pin 60 with 59. * VDDA(1V8): pin 5 with 4; pin 6 with 7; pin 11 with 10; pin 71 with 72; pin 77 with 78; pins
79, 81, 83 with 80, 82, 84; pins 93, 95, 97 with 92, 94, 96 and pin 99 with 98.
* VDDA(3V3): pin 1 with 100 and pin 75 with 76.
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DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4x and 8x interpolating
11. Package outline
HTQFP100: plastic thermal enhanced thin quad flat package; 100 leads; body 14 x 14 x 1 mm; exposed die pad
SOT638-1
c y exposed die pad side X Dh 75 76 51 50 ZE
A
e E HE wM bp pin 1 index Lp L detail X
Eh
A
A2
A1
(A3)
100 1 wM ZD 25 bp D HD
26
e
vM A B vM B
0 scale DIMENSIONS (mm are the original dimensions) A UNIT max. mm 1.2 A1 0.15 0.05 A2 1.05 0.95 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D(1) 14.1 13.9 Dh 7.1 6.1 E(1) 14.1 13.9 Eh 7.1 6.1 e 0.5 HD
10 mm
HE
L 1
Lp 0.75 0.45
v 0.2
w 0.08
y 0.08
ZD(1) ZE(1) 1.15 0.85 1.15 0.85
7 0
16.15 16.15 15.85 15.85
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT638-1 REFERENCES IEC JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 03-04-07 05-02-02
Fig 20. Package outline SOT638-1 (HTQFP100)
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DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4x and 8x interpolating
12. Abbreviations
Table 43. Acronym B CDMA CML CMOS DAC FIR GSM IF IMD3 LISB LMDS LSB LTE LVDS MMDS MSB NCO NMOS PLL SFDR SPI TD-SCDMA UISB WCDMA WiMAX Abbreviations Description Bandwidth Code Division Multiple Access Current Mode Logic Complementary Metal-Oxide Semiconductor Digital-to-Analog Converter Finite Impulse Response Global System for Mobile communications Intermediate Frequency Third-order InterModulation Distortion Lower Intermediate Significant Byte Local Multipoint Distribution Service Least Significant Bit Long Term Evolution Low-Voltage Differential Signaling Multichannel Multipoint Distribution Service Most Significant Bit Numerically Controlled Oscillator Negative Metal-Oxide Semiconductor Phase-Locked Loop Spurious-Free Dynamic Range Serial Peripheral Interface Time Division-Synchronous Code Division Multiple Access Upper Intermediate Significant Byte Wideband Code Division Multiple Access Worldwide Interoperability for Microwave Access
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DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4x and 8x interpolating
13. Glossary
Spurious-Free Dynamic Range (SFDR): -- The ratio between the RMS value of the reconstructed output sine wave and the RMS value of the largest spurious observed (harmonic and non-harmonic, excluding DC component) in the frequency domain. Intermodulation Distortion (IMD): -- From a dual-tone digital input sine wave (these two frequencies being close together), the intermodulation distortion products IMD2 and IMD3 (respectively, second and third-order components) are defined below. IMD2 -- The ratio of the RMS value of either tone to the RMS value of the worst second order intermodulation product. IMD3 -- The ratio of the RMS value of either tone to the RMS value of the worst third order intermodulation product. Restricted Bandwidth Spurious Free Dynamic Range -- The ratio of the RMS value of the reconstructed output sine wave to the RMS value of the noise, including the harmonics, in a given bandwidth centered around foffset.
14. Revision history
Table 44. Revision history Release date 20100310 Data sheet status Preliminary data sheet Change notice Supersedes Document ID DAC1405D750_1
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DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4x and 8x interpolating
15. Legal information
15.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification -- The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.
malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer's third party customer(s) (hereinafter both referred to as "Application"). It is customer's sole responsibility to check whether the NXP Semiconductors product is suitable and fit for the Application planned. Customer has to do all necessary testing for the Application in order to avoid a default of the Application and the product. NXP Semiconductors does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Non-automotive qualified products -- Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications.
(c) NXP B.V. 2010. All rights reserved.
15.3 Disclaimers
Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or
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In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors' warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors' specifications such use shall be solely at customer's own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors' standard warranty and NXP Semiconductors' product specifications.
15.4 Patents
Notice is herewith given that the subject device uses one or more of the following patents and that each of these patents may have corresponding patents in other jurisdictions.
15.5 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
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17. Tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Ordering information . . . . . . . . . . . . . . . . . . . . .2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . .8 Thermal characteristics . . . . . . . . . . . . . . . . . . .8 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .9 Read or Write mode access description . . . . .14 Number of bytes transferred . . . . . . . . . . . . . .14 SPI timing characteristics . . . . . . . . . . . . . . . .15 Register allocation map . . . . . . . . . . . . . . . . . .16 COMMon register (address 00h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .17 TXCFG register (address 01h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .17 PLLCFG register (address 02h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .18 FREQNCO_LSB register (address 03h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 FREQNCO_LISB register (address 04h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 FREQNCO_UISB register (address 05h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 FREQNCO_MSB register (address 06h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 PHINCO_LSB register (address 07h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 PHINCO_MSB register (address 08h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 DAC_A_Cfg_1 register (address 09h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 DAC_A_Cfg_2 register (address 0Ah) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 DAC_A_Cfg_3 register (address 0Bh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Table 22. DAC_B_Cfg_1 register (address 0Ch) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 23. DAC_B_Cfg_2 register (address 0Dh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 24. DAC_B_Cfg_3 register (address 0Eh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 25. DAC_Cfg register (address 0Fh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 26. SYNC_Cfg register (address 10h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 27. DAC_A_Aux_MSB register (address 1Ah) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 28. DAC_A_Aux_LSB register (address 1Bh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 29. DAC_B_Aux_MSB register (address 1Ch) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 30. DAC_B_Aux_LSB register (address 1Dh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 31. Recommended configuration . . . . . . . . . . . . . . 22 Table 32. Mode selection . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 33. Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 34. Sample clock phase and polarity examples . . 25 Table 35. Optimum external PLL timing settings . . . . . . 25 Table 36. Interpolation filter coefficients . . . . . . . . . . . . . 26 Table 37. Inversion filter coefficients . . . . . . . . . . . . . . . . 27 Table 38. DAC transfer function . . . . . . . . . . . . . . . . . . . 28 Table 39. IO(fs) coarse adjustment . . . . . . . . . . . . . . . . . . 29 Table 40. IO(fs) fine adjustment . . . . . . . . . . . . . . . . . . . . 30 Table 41. Digital offset adjustment . . . . . . . . . . . . . . . . . 31 Table 42. Auxiliary DAC transfer function . . . . . . . . . . . . 32 Table 43. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 44. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 39
18. Figures
Fig 1. Fig 2. Fig 3. Fig 4. Fig 5. Fig 6. Fig 7. Fig 8. Fig 9. Fig 10. Fig 11. Fig 12. Fig 13. Fig 14. Fig 15. Fig 16. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . .4 SPI protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 SPI timing diagram . . . . . . . . . . . . . . . . . . . . . . .14 Dual-port mode . . . . . . . . . . . . . . . . . . . . . . . . . .22 Interleaved mode operation . . . . . . . . . . . . . . . . .23 Interleaved mode timing (8x interpolation, latch on rising edge) . . . . . . . . . . . . . . . . . . . . . .23 LVDS clock configuration . . . . . . . . . . . . . . . . . . .24 Interfacing CML to LVDS . . . . . . . . . . . . . . . . . . .24 Input timing diagram when internal PLL bypassed (off) . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Internal reference configuration . . . . . . . . . . . . . .29 Equivalent analog output circuit (one DAC) . . . . .31 1 Vo(p-p) differential output with transformer . . . . .32 2 Vo(p-p) differential output with transformer . . . . .33 An example of a DC interface to a 1.7 VI(cm) AQM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 An example of a DC interface to a 3.3 VI(cm) AQM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Fig 17. An example of a DC interface to a 1.7 VI(cm) AQM using auxiliary DACs . . . . . . . . . . . . . . . . . 34 Fig 18. An example of a DC interface to a 3.3 VI(cm) AQM using auxiliary DACs . . . . . . . . . . . . . . . . . 35 Fig 19. An example of an AC interface to a 0.5 VI(cm) AQM using auxiliary DACs . . . . . . . . . . . . . . . . . 36 Fig 20. Package outline SOT638-1 (HTQFP100) . . . . . . 37
DAC1405D750_1
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 -- 10 March 2010
42 of 43
NXP Semiconductors
DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4x and 8x interpolating
19. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8 8 Thermal characteristics . . . . . . . . . . . . . . . . . . 8 9 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 9 10 Application information. . . . . . . . . . . . . . . . . . 13 10.1 General description . . . . . . . . . . . . . . . . . . . . 13 10.2 Serial peripheral interface. . . . . . . . . . . . . . . . 13 10.2.1 Protocol description . . . . . . . . . . . . . . . . . . . . 13 10.2.2 SPI timing description . . . . . . . . . . . . . . . . . . . 14 10.2.3 Detailed descriptions of registers . . . . . . . . . . 15 10.2.4 Detailed register descriptions . . . . . . . . . . . . . 17 10.2.5 Recommended configuration . . . . . . . . . . . . . 22 10.3 Input data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 10.3.1 Dual-port mode . . . . . . . . . . . . . . . . . . . . . . . . 22 10.3.2 Interleaved mode . . . . . . . . . . . . . . . . . . . . . . 22 10.4 Input clock . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 10.5 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 10.5.1 Timing when using the internal PLL (PLL on) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 10.5.2 Timing when using an external PLL (PLL off) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 10.6 FIR filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 10.7 Quadrature modulator and Numerically Controlled Oscillator . . . . . . . . . . . . . . . . . . . . 26 10.7.1 NCO in 32-bit . . . . . . . . . . . . . . . . . . . . . . . . . 27 10.7.2 Low-power NCO . . . . . . . . . . . . . . . . . . . . . . . 27 10.7.3 Minus_3dB function . . . . . . . . . . . . . . . . . . . . 27 10.8 x / (sin x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10.9 DAC transfer function . . . . . . . . . . . . . . . . . . . 28 10.10 Full-scale current . . . . . . . . . . . . . . . . . . . . . . 28 10.10.1 Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10.10.2 Full-scale current adjustment . . . . . . . . . . . . . 29 10.11 Digital offset adjustment . . . . . . . . . . . . . . . . . 30 10.12 Analog output . . . . . . . . . . . . . . . . . . . . . . . . . 31 10.13 Auxiliary DACs . . . . . . . . . . . . . . . . . . . . . . . . 32 10.14 Output configuration . . . . . . . . . . . . . . . . . . . . 32 10.14.1 Basic output configuration . . . . . . . . . . . . . . . 32 10.14.2 DC interface to an Analog Quadrature Modulator (AQM) . . . . . . . . . . . . . . . . . . . . . . 33 10.14.3 10.15 11 12 13 14 15 15.1 15.2 15.3 15.4 15.5 16 17 18 19 AC interface to an Analog Quadrature Modulator (AQM) . . . . . . . . . . . . . . . . . . . . . . Power and grounding. . . . . . . . . . . . . . . . . . . Package outline. . . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Glossary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Patents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 36 37 38 39 39 40 40 40 40 41 41 41 42 42 43
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 10 March 2010 Document identifier: DAC1405D750_1

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